Two for the price of one

Multi-threading is a long established technology whereby operating system and application code is split into separate streams, or threads.

By using two or more processors, the separate threads can then be processed concurrently to boost overall server performance. A new variation, simultaneous multi-threading (SMT), allows separate code threads to be processed concurrently by just one chip.

Performance is enhanced by sharing on-chip resources, or execution units, which would otherwise be underused.

Introduced on the latest generation of its IA-32 processors (Pentium 4 and Xeon), Hyper-Threading (previously codenamed 'Jackson') is the name given by Intel to its implementation of SMT.

In the Intel architecture, the processor core is largely unchanged, with a single set of execution units, cache, system bus interface and so on.

However, two logical processors are implemented on top of these, each with its own registers and separate Advanced Programmable Interrupt Controller. These are known collectively as the architectural state.

Once the physical processor has been initialised the logical processors can be started and halted independently. They can also process separate code threads like the processors in a conventional multi-processor system, but using the same core to execute the instructions involved.

Intel claims that only 35 per cent of the available on-chip resources are used when running a typical mix of IA-32 instructions and that, with Hyper-Threading enabled, gains of up to 30 per cent in processing speed should be possible.

It also claims that performance gains from Hyper-Threading should scale in much the same way as for conventional multi-processing.

In practice

A major bonus with Intel's implementation of this technology is that very little needs to be done to take advantage of it. Some minor BIOS tweaks are needed, but no changes are required to the host operating system, which sees two processors for each physical one installed.

A single processor, therefore, appears to be a dual-processing MPS system, two chips look like a four-way MPS set up and so on. Operating system code and applications also continue to run as normal.

In the Labs

Because of the lack of compatibility issues, it was easy to run benchmark tests on the new processors in the labs at vnunet.com's sister publication PC Magazine. Intel sent us an early pre-production system fitted with a pair of 2GHz Xeon (512Kb Level 2 cache version) processors with the Hyper-Threading enhancements enabled.

These were accompanied by 512Mb of Rambus memory and a standard EIDE hard disk drive. We tested the system using our WebBench benchmark on our test network of 48 client PCs.

When running a simple suite of static HTML requests, Hyper-Threading had little impact as little processing is required at the web server end. However, when we switched to a suite that uses Secure Socket Layer encryption, we recorded a peak improvement of just under 50 per cent.

These are very impressive results considering that this was on a pre-production implementation. When shipped, Intel is promising new chipsets to further optimise the Hyper-Threading technology.

In the future

Hyper-Threading would appear to have a lot to offer at little cost. However, there could be problems, for example with applications licensed on a per-processor basis.

As for the future, Intel has already demonstrated processors using Hyper-Threading running at clock speeds of up to 3.5GHz. It also plans to refine the technology, although it's likely that such developments will run out of steam by around 2006.

At that time, the company is expected to switch to developing multi-core processors supporting 'real' multi-processing on a chip, something rivals AMD and others are rumoured to be contemplating as an alternative to the SMT approach.

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