AMD's response to Intel Core 2 Duo

AMD started planning multi-core chips as early as 2001.

Its architecture is different from that used in Core, with separate 512KB or 1MB L2 caches for each AMD64 execution core, an on-chip DDR2 memory controller, and a Hypertransport 8Gbits/sec bus rather than the usual front-side bus (FSB).

This structure tightly couples the processor cores and memory subsystem to minimise bottlenecks.

However, the separate and relatively small L2 caches can impact on performance through lack of flexibility, with one cache thrashing while the other is unused, and through data duplication, where one cache slowly accesses main memory even though the data it needs is already in the other.

AMD has acknowledged this criticism by hinting at plans for a shared L3 cache to sit on top of the individual L2 units.

While AMD’s existing range is comparable to Meron, Conroe and Woodcrest, Intel now seems to have the edge in performance and power consumption terms with the Core architecture.

AMD’s next competitive move will be the K8L architecture, set for formal announcement in mid-2007.

It will include new dual-core desktop designs as well as a quad-core server chip.

For the mobile market, a New Mobile Core design will replace Turion 64 X2.

Both forthcoming designs will feature improved floating-point performance, a faster Hypertransport bus and enhanced memory controllers. However, the full feature set remains vague at this stage.

This article is part of a bigger piece on Intel's new Core 2 processors

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